The present invention relates generally to memory devices and, more particularly, to an asymmetric cell and bit design for improving the bit yield of a magnetoresistive random access memory (MRAM) device.
Integrated circuit designers have always sought the ideal semiconductor memory: a device that is randomly accessible, can be written or read very quickly, is non-volatile, but indefinitely alterable, and consumes little power. MRAM technology has been increasingly viewed as offering all these advantages.
An MRAM device typically includes an array of magnetic memory cells. A typical magnetic memory cell has a structure which includes magnetic layers separated by a non-magnetic layer. Magnetic vectors in one magnetic layer, typically referred to as the pinned layer, are magnetically fixed or pinned in one direction. The magnetic vectors of the other magnetic layer, often referred to as the storage or sense layer, are not fixed so that its magnetization direction is free to switch between xe2x80x9cparallelxe2x80x9d and xe2x80x9canti-parallelxe2x80x9d states relative to the pinned layer. In response to the parallel state, the magnetic memory cell will have a low resistance state. Conversely and in response to the anti-parallel state, the magnetic memory cell will have a high resistance state. The MRAM device associates these two resistance states with either a logical xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d bit value.
A logical xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is usually written into the magnetic memory cell by applying external magnetic fields (via an electrical current) that rotate the magnetization direction in the storage layer. Typically, the orientation of magnetization in the storage layer aligns along an axis known as the easy-axis. The external magnetic fields are applied to flip the orientation of magnetization in the storage layer along its easy-axis to either the parallel or anti-parallel orientation with respect to the orientation of magnetization in the pinned layer depending on the desired logic state.
MRAM devices usually include an array of row lines and column lines that are used to apply the external magnetic fields to the magnetic memory cells during writing. The magnetic memory cells are usually located at intersections of the row lines and column lines. A selected magnetic memory cell is usually written by applying electrical currents to the particular row and column lines that intersect at the selected magnetic memory cell.
FIG. 1 illustrates a portion of an array 10 of magnetic memory cells 11 found in the typical MRAM device. The cells 11 are arranged into rows and columns with each row having an associated row line 12 and each column having an associated column line 14. In addition, the cells 11 are arranged with their long axis extending parallel to the row lines 12 and their transverse axis extending parallel to the column lines 14. Referring to FIGS. 1 and 2a, each cell 11 has an easy-axis 19 of magnetization directed parallel with the long axis (length) of the cell and a hard-axis 20 of magnetization directed parallel with the short axis (width) of the cell. Each cell 11 has a column line 14 that generates an easy-axis magnetic field when current is applied through it and a row line 12 that generates a hard-axis magnetic field when current is applied through it. The manner in which currents generate magnetic fields in magnetic memory devices is well known in the art and is not discussed herein.
The magnetic field aligned to the easy-axis is referred to herein as the easy-axis write field while the other field is referred to as the hard-axis write field. It is desired that only the selected magnetic memory cell receives both the easy-axis and hard-axis write fields. Each write field is commonly referred to as a half-select field because individually they cannot switch the contents of cell. In practice, however, the hard-axis write field is usually referred to as the half-select field, while the easy-axis write field is referred to as the switching field.
The bit stored in the selected memory cell is referred to herein as a xe2x80x9cselected bit.xe2x80x9d AR of the remaining memory cells coupled to the column line or row line, which are not the desired selected cell are referred to herein as xe2x80x9cunselected cellsxe2x80x9d and their corresponding bits are xe2x80x9cunselected bits.xe2x80x9d The unselected cells coupled to the particular column line usually receive only the easy-axis write field. Similarly, the unselected cells coupled to the particular row line usually receive only the hard-axis write field. The magnitudes of the easy-axis and hard-axis write fields are usually chosen to be high enough so that the stored bit in the selected magnetic memory cell switches its logic state, but are low enough so that the stored bits in the unselected memory cells, that are subject to only one of the write fields, do not switch. An undesirable switching of a stored bit in an unselected magnetic memory cell (i.e., one that receives only one of the write fields) is commonly referred to as half-select switching.
A serious problem that needs to be overcome in order to build reliable MRAM devices is the distribution of the switching fields that occur in the selected and unselected bits. A distribution of selected or unselected write fields strongly degrades bit yield. This is due to an overlap in the distribution of the write currents between the selected and unselected bits. It has been determined that this problem is attributable in part to the shape of the memory cells.
Referring again to FIG. 2a and as discussed above, the typical memory cell 11 has multiple layers of magnetoresistive material. For example, the illustrated cell 11 includes a first magnetic layer 16 and a second magnetic layer 17, which are separated by a first conducting or insulating spacer layer 18. The stack of magnetic and non-magnetic layers are often patterned into symmetrical shape such as an ellipse, rectangle or hexagon. FIG. 2a illustrates a memory cell 11 with a rectangular shape. In the illustrated rectangular cell 11, the layers 16 and 17 have a magnetization vector 21 that is positioned substantially along the length or easy-axis of the cell 11. The vector 21 is depicted with an arrowhead at each end to represent the two different magnetization directions within the cell 11. As discussed above, the magnetization in one of the layers 16/17 is generally pinned while the magnetization of the other layer 17/16 is free to rotate into either of the two positions represented by the vector 21.
The problem with the shape of the current magnetic memory cell (i.e., ellipse, rectangle, hexagon) is that they are perfectly symmetrical. Any slight deviation from the perfectly symmetrical shape due to, for example, manufacturing process variations can cause a significant change in the magnetic fields and currents required to write a bit into the cells increasing the distribution of write currents within the array. This decreases write margin (i.e., the difference between the write currents of selected and unselected bits), which reduces bit yield.
Accordingly, there is a desire and need for a cell and bit design that increases the write margin and bit yield in an MRAM device.
The present invention provides a design for memory cells of an MRAM device that increases the write margin and bit yield of the MRAM device.
The above and other features and advantages are achieved by providing an asymmetric cell and bit design, rather than a symmetric design, for an MRAM device. The design is asymmetric when reflected about the easy-axis and has a centroid that is displaced from the bit center along the hard-axis. This asymmetry is large enough so that manufacturing process variations do not substantially change the switching fields of the stored bits. In addition, the asymmetry causes the ends of the bits to align in opposite directions in small half-select fields and parallel to each other at large half-select fields, which increases the difference in the switching fields between selected and unselected bits. The combined effect of these two characteristics results in increased bit yield (relative to similarly sized symmetric cells and bits) due to a smaller overlap between selected and unselected bit switching distributions.